1. Field of the Invention
The present invention relates to a mixed-signal integrated circuit, and more particularly to the interconnections in a mixed-signal integrated circuit.
2. Description of the Related Art
Mixed-signal integrated circuits, which incorporate both analog and digital circuitry, have become highly integrated, sometimes comprising an entire system on a chip (SoC). Their analog circuitry typically includes high-precision low-noise capacitors having a polysilicon-insulator-polysilicon (PIP) or metal-insulator-metal (MIM) structure with unit capacitance values in the general range from half a femtofarad to two femtofarads per square micrometer (0.5 fF/μm2 to 2.0 fF/μm2) These capacitors are interconnected to complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), and other types of circuits. At high levels of integration, multiple interconnection layers become necessary, the interconnections being routed on complex paths including both horizontal interconnecting lines and vertical contacts and vias.
Contacts connect circuit elements to horizontal interconnecting lines. A capacitor, for example, is typically connected to a horizontal interconnecting line by multiple contacts, to enable the capacitor to be charged and discharged rapidly.
Vias interconnect horizontal interconnecting lines in different layers. Normally two interconnecting lines are interconnected through a single via. This is particularly true in a highly integrated system-on-a-chip, in which layout space is at a premium.
The processes used to fabricate multilayer interconnections involve much use of ionized gases or plasmas. For example, the interlayer dielectric films that provide electrical insulation between different layers are often deposited by plasma-enhanced chemical vapor deposition (PE-CVD) or high-density plasma chemical vapor deposition (HDP-CVD). Contact holes and via holes are formed in the interlayer dielectric films by plasma etching processes. Plasma etching is also used to fashion horizontal interconnecting lines from metal films.
Since these plasma processes are carried out after the MIM or PIP capacitors have already been formed, some of the electrical charge of the plasma is transferred to the capacitors. Since the capacitors are almost always electrically floating, the charge cannot easily escape to the substrate or otherwise be removed.
As a result, when a contact hole or via hole leading directly or indirectly to a capacitor is formed by plasma etching, considerable charge may already have accumulated in the capacitor. At the instant when the hole is completely opened, or slightly thereafter, the capacitor abruptly discharges its accumulated charge through the hole into the plasma. When the via hole closest to the capacitor on the interconnection path is formed, the entire discharge is typically routed through a single via hole.
The sudden concentrated flow of discharge current through a single via hole can damage the floor of the via hole. If, for example, the floor of the via hole comprises a titanium nitride film formed on the surface of the underlying metal interconnecting line, this film may be oxidized and denitrified by the discharge, as observed in electron microscope studies by the inventor. If such damage occurs, then when the via hole is later filled with metal to form an interconnecting via, the via fails to make good electrical contact with the underlying metal interconnecting line, creating an abnormally high electrical resistance on the signal path. The analog circuit including the capacitor then acquires incorrect operating characteristics, or fails to operate at all. Investigations by the inventor have shown that this problem occurs when the total capacitance of the capacitor is 1700 fF or greater.
Further information will be given in the detailed description of the invention.